Not Applicable.
Not Applicable.
The present embodiments relate to devices including peripheral component interconnect (PCI) buses such as laptop computers, and are more particularly directed to circuits, systems, and methods for efficient wake up operations for controllers for PCI devices.
As computer systems advance in development, various techniques are evolving to produce more power efficient machines. For example, in the instance of portable computers such as laptops and notebook computers, it is desirable to improve power efficiency so that the rechargeable power supply lasts a greater amount of time between recharge periods. Therefore, various techniques have arisen to reduce power consumption in these types of computers, particularly during periods of reduced activity or non-use, such as when the user has not operated the keyboard for a particular amount of time. Power consumption techniques also arise in the context of desktop computers. For example, many users prefer to leave their computers turned on during lengthy periods of non-use, and even overnight for purposes of serving other computers, convenience, receiving facsimile transmissions, or simply to avoid a lengthy boot-up procedure upon returning to the computer the next day. During these periods of non-use, power reduction is also beneficial. Lastly, the combination of portable computers and desktop computers in so-called docking bay configurations also benefits from power adjustments, particularly in instances where the portable computer is removed from the dock, thereby changing the power consumption considerations. These varying configurations each may benefit from improved power performance.
One current approach to power reduction in portable computer systems is directed to operations of devices coupled to the PCI bus. More specifically, different levels of operation are associated with the current PCI standard according to the power considerations for those levels. For example, at level D0, devices connected to the PCI bus are at full operation. In levels D1 and D2, overall voltage and current are not reduced to the PCI-connected devices, but power consumption otherwise may be reduced such as by reducing the clock speed provided to various devices. In a more conservative state of operation referred to as the D3 cold state, the voltage supplied to the PCI-connected devices is referred to as Vaux rather than the VCC level which applies in any of D0 through D2, and during this state the available current to the PCI-connected devices is considerably reduced. This D3 cold state is also sometimes referred to as a deep sleep state. In any event, it is this D3 cold state to which the preferred embodiments are directed by way of example, and thus it is primarily this state and other PCI related principles which are discussed herein.
By way of further background, it is noted that the present PCI standard does not contemplate certain advancements in power reduction circuits and methodology. Specifically, in the context of evolving to the D3 cold state under the state of the art, the PCI specification in its current form creates an inconsistency. Particularly, under current systems using the PCI standard an assertion by the PCI bus of a single active low reset signal may be contemplated to place the PCI-connected units into a deep sleep state. As a result, however, with no additional improvement to the state of the art, this reset signal causes any device connected to receive such signal to operate in the same manner as any ordinary reset. Such a reset typically initializes the device and thereby dears various state and other information in the device. Indeed, either at the same time or immediately after this active low reset, often other PCI bus signals are also asserted active low and which also may clear any information from a device or devices connected to receive those signals. Therefore, if this single reset signal is asserted in an attempt to achieve the D3 cold state, then the PCI-connected units would operate in the same manner as during a reset caused at system start up. Such an approach is unacceptable as detailed below.
While the above PCI operations have proven useful for reset operations, it has been observed that the prior methodology is insufficient given the advancement of the use of so-called PCI power management event (xe2x80x9cPMExe2x80x9d) specifications, and is further inadequate in the mobile computing environment. A PME occurs when a device wishes to wake the system, at least as far as the particular device is concerned, from a deep sleep state. More particularly, in newer technologies supporting PME, each PCI unit and any controller connected between such unit and the PCI bus includes a PME register, and included in that register is an event bit which the corresponding unit sets when it causes a PME to occur. A device also may store information in that register or in an additional register (e.g., a card status change register), where the information identifies the type of event which gives rise to the need to awaken the system from the sleep state. Thus, when a PME occurs, the system may check the PME register of each of the PCI units having such a register and determine from that information which unit caused the PME, and it may further be determined what type of event requires service. For example, if the device in question is a modem that was in a deep sleep state and received an incoming ring during that state, the modem may initially respond by setting its PME event bit to awaken the system insofar as the modem is concerned, and then to respond to the incoming call.
Given the preceding background, the present inventors were faced with the evolution of PME operation and the specifications required of the PCI bus and PCI-compliant devices. In addition, it is has been noted by the present inventors as well as through their efforts in collaboration with others that the state of the art for PCI devices poses conflicts with the advancements of specifications for mobile computers. From this collaboration as well as through the additional input of others, a PCI Bus Power Management Interface Specification for PCI to CardBus Bridges was developed and has imposed certain restrictions on the present inventors and others when considering designs for PCI compliance in mobile computers. More specifically, the PCI Bus Power Management Interface Specification for PCI to CardBus Bridges states that in order for PCI controllers to comply with the specification, the power management event bit as well as the identifier of what caused a PME to occur must be available from the controller upon wake-up from a deep sleep; however, the PCI Bus Power Management Interface Specification for PCI to CardBus Bridges does not provide a mechanism for ensuring that this information is available in this manner, and it also does not address other information which otherwise may be affected during either or both of the deep sleep state or the waking of the PCI device from that state. In view of these considerations, a key drawback has been observed in that the reset operation caused by a PCI reset could effectively prohibit the proper maintenance or availability of PME and related information when it is desired to awaken a PCI device from a deep sleep state. Accordingly, there arises a need to improve upon the prior art and provide a system for more properly accommodating PCI protocol and the PCI Bus Power Management Interface Specification for PCI to CardBus Bridges while supporting the power savings provided by PME operations.
In one preferred embodiment, there is a controller for coupling between a computer bus and one or more units compatible with the bus. The controller comprises a first input for receiving a first reset signal issued from the computer bus, a second input for receiving a second reset signal. The controller further comprises circuitry for storing a first set of information which will be cleared in response to assertion of the first reset signal. Lastly, the controller comprises circuitry for storing a second set of information which will not be cleared in response to assertion of the first reset signal but which will be cleared in response to assertion of the second reset signal. In a described embodiment, the bus is a PCI bus, the first reset signal is a PCI Reset signal, and the second reset signal is an initialization signal. Other circuits, systems, and methods are also described and claimed.